Patent Document 1 (JP2013-115054A) discloses a semiconductor chip which includes a semiconductor substrate having a front surface formed with a plurality of semiconductor elements, an interlevel insulation film provided on the semiconductor substrate, a plurality of electrode pads provided on the interlevel insulation film, and a surface protection film provided on the interlevel insulation film and having pad openings through which the electrode pads are respectively exposed. The electrode pads are respectively connected to bonding wires in a resin package.